The present invention relates, in general, to semiconductors, and more particularly, to methods of forming semiconductor devices and equipment for manufacturing semiconductor wafers and devices.
In the past, the semiconductor industry utilized various methods and equipment for manufacturing semiconductor wafers, such as manufacturing circuits on a semiconductor wafer. For some manufacturing operations, the wafer was placed in a reactor or high-temperature oven to perform some of the manufacturing operation(s). Typically, the semiconductor wafer was placed on a wafer support or wafer carrier, often referred to as a wafer susceptor or susceptor. The semiconductor wafer typically was placed on the susceptor and the susceptor was placed inside the reactor to perform operations such as chemical vapor deposition (CVD) or reactive ion etching (RIE) or epitaxial layer formation or other manufacturing procedures.
Often during the manufacturing operation, defects were formed on certain areas of the semiconductor wafer. These defects reduced the number of good usable die on the semiconductor wafer. Such defects increase the manufacturing cost and reduced the reliability of the semiconductor devices.
Accordingly, it is desirable to have equipment and methods for processing semiconductor wafers and devices that assist in reducing defects on a semiconductor wafer, that assist in increasing the yield of good die from the semiconductor wafer, and that assists in reducing manufacturing cost.
For simplicity and clarity of the illustration(s), elements in the figures are not necessarily to scale, and the same reference numbers in different figures denote the same elements, unless stated otherwise. The drawings described herein are only schematic and are non-limiting. The dimensions and the relative dimensions do not correspond to actual reductions to practice of the invention. Additionally, descriptions and details of well-known steps and elements are omitted for simplicity of the description. It will be appreciated by those skilled in the art that the words during, while, and when as used herein relating to circuit operation are not exact terms that mean an action takes place instantly upon an initiating action but that there may be some small but reasonable delay(s), such as various propagation delays, between the reaction that is initiated by the initial action. Additionally, the term while means that a certain action occurs at least within some portion of a duration of the initiating action. The use of the word approximately or substantially means that a value of an element has a parameter that is expected to be close to a stated value or position. However, as is well known in the art there may be minor variances that prevent the values or positions from being exactly as stated. It is well established in the art that variances of up to at least ten percent (10%) (and up to twenty percent (20%) for semiconductor doping concentrations) are reasonable variances from the ideal goal of exactly as described. The terms first, second, third and the like in the claims or/and in the Detailed Description of the Drawings, as used in a portion of a name of an element are used for distinguishing between similar elements and not necessarily for describing a sequence, either temporally, spatially, in ranking or in any other manner. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments described herein are capable of operation in other sequences than described or illustrated herein.